The present invention is generally related to memory systems for microcomputers, and more particularly to a memory controller for static column mode dynamic random access memories (DRAMs) which significantly improves system performance.
A typical microcomputer system has the central processing unit (CPU) 10 connected to the memory 12 over a bus 14 as shown in FIG. 1. To access data in the memory banks 16, the CPU 10 goes through a memory controller 18. The memory controller 18 performs the task of refreshing the DRAMs, bank interleaving, clocking and handshake protocol with the CPU 10. Some microcomputers also have an instruction and/or data cache 20 to increase system throughput. The cache is a fast memory, and it normally resides on the CPU side of the bus. The control logic associated with the cache attempts to maximize the number of accesses to the cache. An access to the cache is termed a "hit". The main memory is accessed only when the desired word is not available in the cache, i.e. a "miss".
An example of a prior art system is disclosed in U.S. Pat. No. 4,156,290 issued to Lucin Lanza. This patent discloses a random access memory (RAM) composed of a plurality of memory chips, each chip having input and output registers. The memory controller comprises a staticizer register which stores the most significant part of the current address. The output of the register comprises a channel connected to an address comparison circuit and to the inputs of the RAM chips. Each address for the memory comprises a first part which addresses all the words of the memory elements stored in the address identified by the first part. All the addressed words are stored in corresponding address registers. The second part of the address enables the selection of the output register associated therewith. With this procedure, the reading operation for a block of information requires only one memory access time plus the read time of the output registers.
U.S. Pat. No. 4,382,278 to Daren R. Appelt discloses a computer system wherein a plurality of registers and at least one workspace is provided in main memory. In addition, there is a workspace cache memory made up of registers within the central processing unit (CPU). Those registers correspond to the registers in the workspace in the main memory. Computer operations are implemented using the contents of the workspace cache registers whose contents are transmitted to the corresponding working registers in the workspace of the main memory in the event of a context switch. The architecture of this workspace system achieves high speed register-to-register operations and high speed context switching.
DRAMs with static column mode now offered by some manufacturers represents a new trend in dynamic memories. They have an on-chip static buffer for storing an entire row (256 bits for a 64 Kbit DRAM chip). A 64K DRAM has 256 rows of 256 bits each. A 256K DRAM has 512 rows of 512 bits each, whereas a 64K by 4 DRAM has 4 times 256 rows of 256 bits. Once the row is stored in this buffer, any bit can be accessed (read or written) in this row very fast. For a 130 ns. cycle time DRAM, the cycle time from the buffered row is only 40 ns. as illustrated in FIG. 2.